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authorTuan Phan <tphan@ventanamicro.com>2023-10-04 11:34:26 -0700
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2023-10-17 07:44:25 +0000
commit772ec92577a8c786b6c9f8643fa60f1cf893bcd9 (patch)
treecd9abd9ed7455fdb29587910e5aa938aadf7e45d /ArmPkg/Drivers/ArmPsciMpServicesDxe/ArmPsciMpServicesDxe.c
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UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Introduce a PCD to control the maximum SATP mode that MMU allowed to use. This PCD helps RISC-V platform set bare or minimum SATP mode during bring up to debug memory map issue. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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