diff options
author | Ronald Cron <ronald.cron@arm.com> | 2014-08-19 13:22:20 +0000 |
---|---|---|
committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-08-19 13:22:20 +0000 |
commit | 62d441fb17d59958bf00c4a1f3b52bf6a0b40b24 (patch) | |
tree | 4802e79aba1b4679a1ef440127192c36787c80ab /ArmPkg/Drivers | |
parent | 01ce3538131437b2deae873ce5aeccf05951ebac (diff) | |
download | edk2-62d441fb17d59958bf00c4a1f3b52bf6a0b40b24.tar.gz edk2-62d441fb17d59958bf00c4a1f3b52bf6a0b40b24.tar.bz2 edk2-62d441fb17d59958bf00c4a1f3b52bf6a0b40b24.zip |
ARM Packages: Corrected non-DOS line endings
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15832 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Drivers')
-rw-r--r-- | ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 | ||||
-rw-r--r-- | ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c index 41e970bc49..717b18b9e6 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -157,7 +157,7 @@ ArmGicDisableDistributor ( // Disable Gic Distributor
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x0);
}
- +
VOID
EFIAPI
ArmGicEnableInterruptInterface (
diff --git a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c b/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c index 8000626126..22c56a347b 100644 --- a/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c +++ b/ArmPkg/Drivers/CpuDxe/ArmV6/Exception.c @@ -208,7 +208,7 @@ InitializeExceptions ( //Note: On ARM processor with the Security Extension, the Vector Table can be located anywhere in the memory.
// The Vector Base Address Register defines the location
ArmWriteVBar (PcdGet32(PcdCpuVectorBaseAddress));
- } else { + } else {
// The Vector table must be 32-byte aligned
if (((UINT32)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) != 0) {
ASSERT (0);
|