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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-18 15:59:42 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-18 15:59:42 +0000 |
| commit | 42dc8026a8711315652936ffd334a4752bbd5d2e (patch) | |
| tree | debcbe15b7e3150333bc9cbfa92016c7698e8144 /ArmPkg/Include | |
| parent | 65ceda9173e688a42a3e74c0c94f4dffc569029c (diff) | |
| download | edk2-42dc8026a8711315652936ffd334a4752bbd5d2e.tar.gz edk2-42dc8026a8711315652936ffd334a4752bbd5d2e.tar.bz2 edk2-42dc8026a8711315652936ffd334a4752bbd5d2e.zip | |
ArmPkg/ArmV7Lib: fix definition of TTBR_NON_INNER_CACHEABLE
The definition of TTBR_NON_INNER_CACHEABLE should be bit 0 cleared, not
bit 0 set. Furthermore, the name is inconsistent with the other definitions
so rename it to TTBR_INNER_NON_CACHEABLE.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18898 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Include')
| -rw-r--r-- | ArmPkg/Include/Chipset/ArmV7Mmu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h index f612154bad..7fafc888fe 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -23,7 +23,7 @@ #define TTBR_SHAREABLE BIT1
#define TTBR_NON_SHAREABLE 0
#define TTBR_INNER_CACHEABLE BIT0
-#define TTBR_NON_INNER_CACHEABLE BIT0
+#define TTBR_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_NON_CACHEABLE 0
#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
|