ArmPkg: Tidy GIC code before changes.

This change is purely cosmetic, to tidy some code before change.
Mods involve:
    Re-order #includes
    Reformat comments.
    Use ns consistently (always "100ns" not sometimes "100 nS")
    Split overlength code lines.
    Make protocol functions STATIC.
    Remove "Horor vacui" comments.
    Rationalize GIC register address calculations
    Replace explicit test and assert with ASSERT_EFI_ERROR.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

1 files changed, 7 insertions, 16 deletions

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 4364f3ffef..a4ede82bc6 100644
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -1,6 +1,6 @@
 /** @file

 *

-*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.

+*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.

 *

 *  This program and the accompanying materials

 *  are licensed and made available under the terms and conditions of the BSD License

@@ -17,9 +17,7 @@
 

 #include <Library/ArmGicArchLib.h>

 

-//

 // GIC Distributor

-//

 #define ARM_GIC_ICDDCR          0x000 // Distributor Control Register

 #define ARM_GIC_ICDICTR         0x004 // Interrupt Controller Type Register

 #define ARM_GIC_ICDIIDR         0x008 // Implementer Identification Register

@@ -51,9 +49,7 @@
 #define ARM_GIC_ICDDCR_ARE      (1 << 4) // Affinity Routing Enable (ARE)

 #define ARM_GIC_ICDDCR_DS       (1 << 6) // Disable Security (DS)

 

-//

 // GIC Redistributor

-//

 

 #define ARM_GICR_CTLR_FRAME_SIZE    SIZE_64KB

 #define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB

@@ -65,9 +61,7 @@
 #define ARM_GICR_ISENABLER      0x0100  // Interrupt Set-Enable Registers

 #define ARM_GICR_ICENABLER      0x0180  // Interrupt Clear-Enable Registers

 

-//

 // GIC Cpu interface

-//

 #define ARM_GIC_ICCICR          0x00  // CPU Interface Control Register

 #define ARM_GIC_ICCPMR          0x04  // Interrupt Priority Mask Register

 #define ARM_GIC_ICCBPR          0x08  // Binary Point Register

@@ -104,9 +98,7 @@ ArmGicGetInterfaceIdentification (
   IN  INTN          GicInterruptInterfaceBase

   );

 

-//

 // GIC Secure interfaces

-//

 VOID

 EFIAPI

 ArmGicSetupNonSecure (

@@ -170,7 +162,8 @@ ArmGicSendSgiTo (
  * in the GICv3 the register value is only the InterruptId.

  *

  * @param GicInterruptInterfaceBase   Base Address of the GIC CPU Interface

- * @param InterruptId                 InterruptId read from the Interrupt Acknowledge Register

+ * @param InterruptId                 InterruptId read from the Interrupt

+ *                                    Acknowledge Register

  *

  * @retval value returned by the Interrupt Acknowledge Register

  *

@@ -220,12 +213,12 @@ ArmGicIsInterruptEnabled (
   IN UINTN                  Source

   );

 

-//

 // GIC revision 2 specific declarations

-//

 

-// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)

-#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))

+// Interrupts from 1020 to 1023 are considered as special interrupts

+// (eg: spurious interrupts)

+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) \

+          (((Interrupt) >= 1020) && ((Interrupt) <= 1023))

 

 VOID

 EFIAPI

@@ -260,9 +253,7 @@ ArmGicV2EndOfInterrupt (
   IN UINTN                  Source

   );

 

-//

 // GIC revision 3 specific declarations

-//

 

 #define ICC_SRE_EL2_SRE         (1 << 0)