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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2020-03-05 13:36:14 +0100 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-03-05 21:08:30 +0000 |
| commit | a17add32c2466d2185073b3d4ce7a03a3374a692 (patch) | |
| tree | 69383d220e5602150cd1af89e5a3e5b87219b756 /ArmPkg/Library/ArmCacheMaintenanceLib | |
| parent | a2ab46adbc6184248878eba3e3c479a3f253ba27 (diff) | |
| download | edk2-a17add32c2466d2185073b3d4ce7a03a3374a692.tar.gz edk2-a17add32c2466d2185073b3d4ce7a03a3374a692.tar.bz2 edk2-a17add32c2466d2185073b3d4ce7a03a3374a692.zip | |
ArmPkg/ArmMmuLib ARM: simplify assignment of TTBR0 system register
The expression passed into ArmSetTTBR0 () in ArmConfigureMmu() is
sub-optimal at several levels:
- TranslationTable is already aligned, and if it wasn't, doing it
here wouldn't help
- TTBRAttributes is guaranteed not to have any bits set outside of
the 0x7f mask, so the mask operation is pointless as well,
- an additional (UINTN) cast for good measure is also not needed.
So simplify the expression.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Diffstat (limited to 'ArmPkg/Library/ArmCacheMaintenanceLib')
0 files changed, 0 insertions, 0 deletions