ARM Packages: Removed trailing spaces

Trailing spaces create issue/warning when generating/applying patches.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ronald Cron <ronald.cron@arm.com>
Reviewed-By: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15833 6f19259b-4bc3-4df7-8a09-765794883524

1 files changed, 16 insertions, 16 deletions

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index 1a5d982022..d035ff3caa 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -2,18 +2,18 @@
 *  File managing the MMU for ARMv7 architecture

 *

 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.

-*  

-*  This program and the accompanying materials                          

-*  are licensed and made available under the terms and conditions of the BSD License         

-*  which accompanies this distribution.  The full text of the license may be found at        

-*  http://opensource.org/licenses/bsd-license.php                                            

 *

-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+*  This program and the accompanying materials

+*  are licensed and made available under the terms and conditions of the BSD License

+*  which accompanies this distribution.  The full text of the license may be found at

+*  http://opensource.org/licenses/bsd-license.php

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

 *

 **/

 

-#include <Uefi.h> 

+#include <Uefi.h>

 #include <Chipset/ArmV7.h>

 #include <Library/BaseMemoryLib.h>

 #include <Library/MemoryAllocationLib.h>

@@ -145,7 +145,7 @@ FillTranslationTable (
   UINT32  Attributes;

   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;

   UINT32  RemainLength = MemoryRegion->Length;

-  

+

   ASSERT(MemoryRegion->Length > 0);

 

   switch (MemoryRegion->Attributes) {

@@ -177,7 +177,7 @@ FillTranslationTable (
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);

       break;

   }

-  

+

   // Get the first section entry for this mapping

   SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);

 

@@ -231,7 +231,7 @@ ArmConfigureMmu (
   if (TranslationTableBase != NULL) {

     *TranslationTableBase = TranslationTable;

   }

-  

+

   if (TranslationTableSize != NULL) {

     *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;

   }

@@ -251,13 +251,13 @@ ArmConfigureMmu (
   }

 

   // Translate the Memory Attributes into Translation Table Register Attributes

-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || 

+  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||

       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {

     TTBRAttributes = TTBR_NON_CACHEABLE;

-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || 

+  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||

       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {

     TTBRAttributes = TTBR_WRITE_BACK_ALLOC;

-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || 

+  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||

       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {

     TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;

   } else {

@@ -278,7 +278,7 @@ ArmConfigureMmu (
   ArmInvalidateInstructionCache ();

 

   ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));

-    

+

   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |

                              DOMAIN_ACCESS_CONTROL_NONE(14) |

                              DOMAIN_ACCESS_CONTROL_NONE(13) |

@@ -295,7 +295,7 @@ ArmConfigureMmu (
                              DOMAIN_ACCESS_CONTROL_NONE( 2) |

                              DOMAIN_ACCESS_CONTROL_NONE( 1) |

                              DOMAIN_ACCESS_CONTROL_MANAGER(0));

-    

+

   ArmEnableInstructionCache();

   ArmEnableDataCache();

   ArmEnableMmu();