ARM Packages: Fixed line endings

This large code change only modifies the line endings to be CRLF to be
compliant with the EDK2 coding convention document.



git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14088 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 539 insertions, 539 deletions

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
index 7835b414c0..478a5da695 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7ArchTimer.c
@@ -1,275 +1,275 @@
-/** @file
-*
-*  Copyright (c) 2011, ARM Limited. All rights reserved.
-*  
-*  This program and the accompanying materials                          
-*  are licensed and made available under the terms and conditions of the BSD License         
-*  which accompanies this distribution.  The full text of the license may be found at        
-*  http://opensource.org/licenses/bsd-license.php                                            
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
-*
-**/
-
-#include <Uefi.h> 
-#include <Chipset/ArmV7.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include "ArmV7Lib.h"
-#include "ArmLibPrivate.h"
-#include <Library/ArmV7ArchTimerLib.h>
-
-VOID
-EFIAPI
-ArmArchTimerReadReg (
-    IN   ARM_ARCH_TIMER_REGS   Reg,
-    OUT  VOID                  *DstBuf
-    )
-{
-  // Check if the Generic/Architecture timer is implemented
-  if (ArmIsArchTimerImplemented ()) {
-
-    switch (Reg) {
-
-    case CntFrq:
-      *((UINTN *)DstBuf) = ArmReadCntFrq ();
-      break;
-
-    case CntPct:
-      *((UINT64 *)DstBuf) = ArmReadCntPct ();
-      break;
-
-    case CntkCtl:
-      *((UINTN *)DstBuf) = ArmReadCntkCtl();
-      break;
-
-    case CntpTval:
-      *((UINTN *)DstBuf) = ArmReadCntpTval ();
-      break;
-
-    case CntpCtl:
-      *((UINTN *)DstBuf) = ArmReadCntpCtl ();
-      break;
-
-    case CntvTval:
-      *((UINTN *)DstBuf) = ArmReadCntvTval ();
-      break;
-
-    case CntvCtl:
-      *((UINTN *)DstBuf) = ArmReadCntvCtl ();
-      break;
-
-    case CntvCt:
-      *((UINT64 *)DstBuf) = ArmReadCntvCt ();
-      break;
-
-    case CntpCval:
-      *((UINT64 *)DstBuf) = ArmReadCntpCval ();
-      break;
-
-    case CntvCval:
-      *((UINT64 *)DstBuf) = ArmReadCntvCval ();
-      break;
-
-    case CntvOff:
-      *((UINT64 *)DstBuf) = ArmReadCntvOff ();
-      break;
-
-    case CnthCtl:
-    case CnthpTval:
-    case CnthpCtl:
-    case CnthpCval:
-    DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
-      break;
-
-    default:
-      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
-    }
-  } else {
-    DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
-    ASSERT (0);
-  }
-}
-
-VOID
-EFIAPI
-ArmArchTimerWriteReg (
-    IN   ARM_ARCH_TIMER_REGS   Reg,
-    IN   VOID                  *SrcBuf
-    )
-{
-  // Check if the Generic/Architecture timer is implemented
-  if (ArmIsArchTimerImplemented ()) {
-
-    switch (Reg) {
-
-    case CntFrq:
-      ArmWriteCntFrq (*((UINTN *)SrcBuf));
-      break;
-
-    case CntPct:
-      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));
-      break;
-
-    case CntkCtl:
-      ArmWriteCntkCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntpTval:
-      ArmWriteCntpTval (*((UINTN *)SrcBuf));
-      break;
-
-    case CntpCtl:
-      ArmWriteCntpCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvTval:
-      ArmWriteCntvTval (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvCtl:
-      ArmWriteCntvCtl (*((UINTN *)SrcBuf));
-      break;
-
-    case CntvCt:
-      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));
-      break;
-
-    case CntpCval:
-      ArmWriteCntpCval (*((UINT64 *)SrcBuf) );
-      break;
-
-    case CntvCval:
-      ArmWriteCntvCval (*((UINT64 *)SrcBuf) );
-      break;
-
-    case CntvOff:
-      ArmWriteCntvOff (*((UINT64 *)SrcBuf));
-      break;
-
-    case CnthCtl:
-    case CnthpTval:
-    case CnthpCtl:
-    case CnthpCval:
-      DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));
-      break;
-
-    default:
-      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));
-    }
-  } else {
-    DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));
-    ASSERT (0);
-  }
-}
-
-VOID
-EFIAPI
-ArmArchTimerEnableTimer (
-    VOID
-    )
-{
-  UINTN TimerCtrlReg;
-
-  ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
-  TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
-  ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
-}
-
-VOID
-EFIAPI
-ArmArchTimerDisableTimer (
-    VOID
-    )
-{
-  UINTN TimerCtrlReg;
-
-  ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);
-  TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
-  ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);
-}
-
-VOID
-EFIAPI
-ArmArchTimerSetTimerFreq (
-    IN   UINTN  FreqInHz
-    )
-{
-  ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);
-}
-
-UINTN
-EFIAPI
-ArmArchTimerGetTimerFreq (
-    VOID
-    )
-{
-  UINTN ArchTimerFreq = 0;
-  ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);
-  return ArchTimerFreq;
-}
-
-UINTN
-EFIAPI
-ArmArchTimerGetTimerVal (
-    VOID
-    )
-{
-  UINTN ArchTimerVal;
-  ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);
-  return ArchTimerVal;
-}
-
-
-VOID
-EFIAPI
-ArmArchTimerSetTimerVal (
-    IN   UINTN   Val
-    )
-{
-  ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);
-}
-
-UINT64
-EFIAPI
-ArmArchTimerGetSystemCount (
-    VOID
-    )
-{
-  UINT64 SystemCount;
-  ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);
-  return SystemCount;
-}
-
-UINTN
-EFIAPI
-ArmArchTimerGetTimerCtrlReg (
-    VOID
-    )
-{
-  UINTN  Val;
-  ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);
-  return Val;
-}
-
-VOID
-EFIAPI
-ArmArchTimerSetTimerCtrlReg (
-    UINTN Val
-    )
-{
-  ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);
-}
-
-VOID
-EFIAPI
-ArmArchTimerSetCompareVal (
-    IN   UINT64   Val
-    )
-{
-  ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);
-}
+/** @file

+*

+*  Copyright (c) 2011, ARM Limited. All rights reserved.

+*  

+*  This program and the accompanying materials                          

+*  are licensed and made available under the terms and conditions of the BSD License         

+*  which accompanies this distribution.  The full text of the license may be found at        

+*  http://opensource.org/licenses/bsd-license.php                                            

+*

+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     

+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             

+*

+**/

+

+#include <Uefi.h> 

+#include <Chipset/ArmV7.h>

+#include <Library/BaseMemoryLib.h>

+#include <Library/MemoryAllocationLib.h>

+#include <Library/ArmLib.h>

+#include <Library/BaseLib.h>

+#include <Library/DebugLib.h>

+#include "ArmV7Lib.h"

+#include "ArmLibPrivate.h"

+#include <Library/ArmV7ArchTimerLib.h>

+

+VOID

+EFIAPI

+ArmArchTimerReadReg (

+    IN   ARM_ARCH_TIMER_REGS   Reg,

+    OUT  VOID                  *DstBuf

+    )

+{

+  // Check if the Generic/Architecture timer is implemented

+  if (ArmIsArchTimerImplemented ()) {

+

+    switch (Reg) {

+

+    case CntFrq:

+      *((UINTN *)DstBuf) = ArmReadCntFrq ();

+      break;

+

+    case CntPct:

+      *((UINT64 *)DstBuf) = ArmReadCntPct ();

+      break;

+

+    case CntkCtl:

+      *((UINTN *)DstBuf) = ArmReadCntkCtl();

+      break;

+

+    case CntpTval:

+      *((UINTN *)DstBuf) = ArmReadCntpTval ();

+      break;

+

+    case CntpCtl:

+      *((UINTN *)DstBuf) = ArmReadCntpCtl ();

+      break;

+

+    case CntvTval:

+      *((UINTN *)DstBuf) = ArmReadCntvTval ();

+      break;

+

+    case CntvCtl:

+      *((UINTN *)DstBuf) = ArmReadCntvCtl ();

+      break;

+

+    case CntvCt:

+      *((UINT64 *)DstBuf) = ArmReadCntvCt ();

+      break;

+

+    case CntpCval:

+      *((UINT64 *)DstBuf) = ArmReadCntpCval ();

+      break;

+

+    case CntvCval:

+      *((UINT64 *)DstBuf) = ArmReadCntvCval ();

+      break;

+

+    case CntvOff:

+      *((UINT64 *)DstBuf) = ArmReadCntvOff ();

+      break;

+

+    case CnthCtl:

+    case CnthpTval:

+    case CnthpCtl:

+    case CnthpCval:

+    DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));

+      break;

+

+    default:

+      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));

+    }

+  } else {

+    DEBUG ((EFI_D_ERROR, "Attempt to read ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));

+    ASSERT (0);

+  }

+}

+

+VOID

+EFIAPI

+ArmArchTimerWriteReg (

+    IN   ARM_ARCH_TIMER_REGS   Reg,

+    IN   VOID                  *SrcBuf

+    )

+{

+  // Check if the Generic/Architecture timer is implemented

+  if (ArmIsArchTimerImplemented ()) {

+

+    switch (Reg) {

+

+    case CntFrq:

+      ArmWriteCntFrq (*((UINTN *)SrcBuf));

+      break;

+

+    case CntPct:

+      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTPCT \n"));

+      break;

+

+    case CntkCtl:

+      ArmWriteCntkCtl (*((UINTN *)SrcBuf));

+      break;

+

+    case CntpTval:

+      ArmWriteCntpTval (*((UINTN *)SrcBuf));

+      break;

+

+    case CntpCtl:

+      ArmWriteCntpCtl (*((UINTN *)SrcBuf));

+      break;

+

+    case CntvTval:

+      ArmWriteCntvTval (*((UINTN *)SrcBuf));

+      break;

+

+    case CntvCtl:

+      ArmWriteCntvCtl (*((UINTN *)SrcBuf));

+      break;

+

+    case CntvCt:

+      DEBUG ((EFI_D_ERROR, "Can't write to Read Only Register: CNTVCT \n"));

+      break;

+

+    case CntpCval:

+      ArmWriteCntpCval (*((UINT64 *)SrcBuf) );

+      break;

+

+    case CntvCval:

+      ArmWriteCntvCval (*((UINT64 *)SrcBuf) );

+      break;

+

+    case CntvOff:

+      ArmWriteCntvOff (*((UINT64 *)SrcBuf));

+      break;

+

+    case CnthCtl:

+    case CnthpTval:

+    case CnthpCtl:

+    case CnthpCval:

+      DEBUG ((EFI_D_ERROR, "The register is related to Hypervisor Mode. Can't perform requested operation\n "));

+      break;

+

+    default:

+      DEBUG ((EFI_D_ERROR, "Unknown ARM Generic Timer register %x. \n ", Reg));

+    }

+  } else {

+    DEBUG ((EFI_D_ERROR, "Attempt to write to ARM Generic Timer registers. But ARM Generic Timer extension is not implemented \n "));

+    ASSERT (0);

+  }

+}

+

+VOID

+EFIAPI

+ArmArchTimerEnableTimer (

+    VOID

+    )

+{

+  UINTN TimerCtrlReg;

+

+  ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);

+  TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;

+  ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);

+}

+

+VOID

+EFIAPI

+ArmArchTimerDisableTimer (

+    VOID

+    )

+{

+  UINTN TimerCtrlReg;

+

+  ArmArchTimerReadReg (CntpCtl, (VOID *)&TimerCtrlReg);

+  TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;

+  ArmArchTimerWriteReg (CntpCtl, (VOID *)&TimerCtrlReg);

+}

+

+VOID

+EFIAPI

+ArmArchTimerSetTimerFreq (

+    IN   UINTN  FreqInHz

+    )

+{

+  ArmArchTimerWriteReg (CntFrq, (VOID *)&FreqInHz);

+}

+

+UINTN

+EFIAPI

+ArmArchTimerGetTimerFreq (

+    VOID

+    )

+{

+  UINTN ArchTimerFreq = 0;

+  ArmArchTimerReadReg (CntFrq, (VOID *)&ArchTimerFreq);

+  return ArchTimerFreq;

+}

+

+UINTN

+EFIAPI

+ArmArchTimerGetTimerVal (

+    VOID

+    )

+{

+  UINTN ArchTimerVal;

+  ArmArchTimerReadReg (CntpTval, (VOID *)&ArchTimerVal);

+  return ArchTimerVal;

+}

+

+

+VOID

+EFIAPI

+ArmArchTimerSetTimerVal (

+    IN   UINTN   Val

+    )

+{

+  ArmArchTimerWriteReg (CntpTval, (VOID *)&Val);

+}

+

+UINT64

+EFIAPI

+ArmArchTimerGetSystemCount (

+    VOID

+    )

+{

+  UINT64 SystemCount;

+  ArmArchTimerReadReg (CntPct, (VOID *)&SystemCount);

+  return SystemCount;

+}

+

+UINTN

+EFIAPI

+ArmArchTimerGetTimerCtrlReg (

+    VOID

+    )

+{

+  UINTN  Val;

+  ArmArchTimerReadReg (CntpCtl, (VOID *)&Val);

+  return Val;

+}

+

+VOID

+EFIAPI

+ArmArchTimerSetTimerCtrlReg (

+    UINTN Val

+    )

+{

+  ArmArchTimerWriteReg (CntpCtl, (VOID *)&Val);

+}

+

+VOID

+EFIAPI

+ArmArchTimerSetCompareVal (

+    IN   UINT64   Val

+    )

+{

+  ArmArchTimerWriteReg (CntpCval, (VOID *)&Val);

+}

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
index d9cf8826ce..cc5074bfc2 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c
@@ -1,264 +1,264 @@
-/** @file
-
-  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
-  
-  This program and the accompanying materials
-  are licensed and made available under the terms and conditions of the BSD License
-  which accompanies this distribution.  The full text of the license may be found at
-  http://opensource.org/licenses/bsd-license.php
-
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-#include <Uefi.h>
-#include <Chipset/ArmV7.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/IoLib.h>
-#include "ArmV7Lib.h"
-#include "ArmLibPrivate.h"
-
-ARM_CACHE_TYPE
-EFIAPI
-ArmCacheType (
-  VOID
-  )
-{
-  return ARM_CACHE_TYPE_WRITE_BACK;
-}
-
-ARM_CACHE_ARCHITECTURE
-EFIAPI
-ArmCacheArchitecture (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-
-  return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me
-}
-
-BOOLEAN
-EFIAPI
-ArmDataCachePresent (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-  
-  if ((CLIDR & 0x2) == 0x2) {
-    // Instruction cache exists
-    return TRUE;
-  }
-  if ((CLIDR & 0x7) == 0x4) {
-    // Unified cache
-    return TRUE;
-  }
-  
-  return FALSE;
-}
-  
-UINTN
-EFIAPI
-ArmDataCacheSize (
-  VOID
-  )
-{
-  UINT32 NumSets;
-  UINT32 Associativity;
-  UINT32 LineSize;
-  UINT32 CCSIDR = ReadCCSIDR (0);
-  
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
-
-  // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;      
-}
-  
-UINTN
-EFIAPI
-ArmDataCacheAssociativity (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0);
-
-  return ((CCSIDR >> 3) & 0x3ff) + 1;
-}
-  
-UINTN
-ArmDataCacheSets (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0);
-  
-  return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmDataCacheLineLength (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (0) & 7;
-
-  // * 4 converts to bytes
-  return (1 << (CCSIDR + 2)) * 4;
-}
-  
-BOOLEAN
-EFIAPI
-ArmInstructionCachePresent (
-  VOID
-  )
-{
-  UINT32 CLIDR = ReadCLIDR ();
-  
-  if ((CLIDR & 1) == 1) {
-    // Instruction cache exists
-    return TRUE;
-  }
-  if ((CLIDR & 0x7) == 0x4) {
-    // Unified cache
-    return TRUE;
-  }
-  
-  return FALSE;
-}
-  
-UINTN
-EFIAPI
-ArmInstructionCacheSize (
-  VOID
-  )
-{
-  UINT32 NumSets;
-  UINT32 Associativity;
-  UINT32 LineSize;
-  UINT32 CCSIDR = ReadCCSIDR (1);
-  
-  LineSize      = (1 << ((CCSIDR & 0x7) + 2));
-  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;
-  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;
-
-  // LineSize is in words (4 byte chunks)
-  return  NumSets * Associativity * LineSize * 4;      
-}
-  
-UINTN
-EFIAPI
-ArmInstructionCacheAssociativity (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1);
-
-  return ((CCSIDR >> 3) & 0x3ff) + 1;
-//  return 4;
-}
-  
-UINTN
-EFIAPI
-ArmInstructionCacheSets (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1);
-  
-  return ((CCSIDR >> 13) & 0x7fff) + 1;
-}
-
-UINTN
-EFIAPI
-ArmInstructionCacheLineLength (
-  VOID
-  )
-{
-  UINT32 CCSIDR = ReadCCSIDR (1) & 7;
-
-  // * 4 converts to bytes
-  return (1 << (CCSIDR + 2)) * 4;
-
-//  return 64;
-}
-
-
-VOID
-ArmV7DataCacheOperation (
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
-  )
-{
-  UINTN     SavedInterruptState;
-
-  SavedInterruptState = ArmGetInterruptState ();
-  ArmDisableInterrupts ();
-  
-  ArmV7AllDataCachesOperation (DataCacheOperation);
-  
-  ArmDrainWriteBuffer ();
-  
-  if (SavedInterruptState) {
-    ArmEnableInterrupts ();
-  }
-}
-
-
-VOID
-ArmV7PoUDataCacheOperation (
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation
-  )
-{
-  UINTN     SavedInterruptState;
-
-  SavedInterruptState = ArmGetInterruptState ();
-  ArmDisableInterrupts ();
-  
-  ArmV7PerformPoUDataCacheOperation (DataCacheOperation);
-  
-  ArmDrainWriteBuffer ();
-  
-  if (SavedInterruptState) {
-    ArmEnableInterrupts ();
-  }
-}
-
-VOID
-EFIAPI
-ArmInvalidateDataCache (
-  VOID
-  )
-{
-  ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanInvalidateDataCache (
-  VOID
-  )
-{
-  ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCache (
-  VOID
-  )
-{
-  ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
-
-VOID
-EFIAPI
-ArmCleanDataCacheToPoU (
-  VOID
-  )
-{
-  ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);
-}
+/** @file

+

+  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

+  

+  This program and the accompanying materials

+  are licensed and made available under the terms and conditions of the BSD License

+  which accompanies this distribution.  The full text of the license may be found at

+  http://opensource.org/licenses/bsd-license.php

+

+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

+

+**/

+#include <Uefi.h>

+#include <Chipset/ArmV7.h>

+#include <Library/ArmLib.h>

+#include <Library/BaseLib.h>

+#include <Library/IoLib.h>

+#include "ArmV7Lib.h"

+#include "ArmLibPrivate.h"

+

+ARM_CACHE_TYPE

+EFIAPI

+ArmCacheType (

+  VOID

+  )

+{

+  return ARM_CACHE_TYPE_WRITE_BACK;

+}

+

+ARM_CACHE_ARCHITECTURE

+EFIAPI

+ArmCacheArchitecture (

+  VOID

+  )

+{

+  UINT32 CLIDR = ReadCLIDR ();

+

+  return (ARM_CACHE_ARCHITECTURE)CLIDR; // BugBug Fix Me

+}

+

+BOOLEAN

+EFIAPI

+ArmDataCachePresent (

+  VOID

+  )

+{

+  UINT32 CLIDR = ReadCLIDR ();

+  

+  if ((CLIDR & 0x2) == 0x2) {

+    // Instruction cache exists

+    return TRUE;

+  }

+  if ((CLIDR & 0x7) == 0x4) {

+    // Unified cache

+    return TRUE;

+  }

+  

+  return FALSE;

+}

+  

+UINTN

+EFIAPI

+ArmDataCacheSize (

+  VOID

+  )

+{

+  UINT32 NumSets;

+  UINT32 Associativity;

+  UINT32 LineSize;

+  UINT32 CCSIDR = ReadCCSIDR (0);

+  

+  LineSize      = (1 << ((CCSIDR & 0x7) + 2));

+  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;

+  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;

+

+  // LineSize is in words (4 byte chunks)

+  return  NumSets * Associativity * LineSize * 4;      

+}

+  

+UINTN

+EFIAPI

+ArmDataCacheAssociativity (

+  VOID

+  )

+{

+  UINT32 CCSIDR = ReadCCSIDR (0);

+

+  return ((CCSIDR >> 3) & 0x3ff) + 1;

+}

+  

+UINTN

+ArmDataCacheSets (

+  VOID

+  )

+{

+  UINT32 CCSIDR = ReadCCSIDR (0);

+  

+  return ((CCSIDR >> 13) & 0x7fff) + 1;

+}

+

+UINTN

+EFIAPI

+ArmDataCacheLineLength (

+  VOID

+  )

+{

+  UINT32 CCSIDR = ReadCCSIDR (0) & 7;

+

+  // * 4 converts to bytes

+  return (1 << (CCSIDR + 2)) * 4;

+}

+  

+BOOLEAN

+EFIAPI

+ArmInstructionCachePresent (

+  VOID

+  )

+{

+  UINT32 CLIDR = ReadCLIDR ();

+  

+  if ((CLIDR & 1) == 1) {

+    // Instruction cache exists

+    return TRUE;

+  }

+  if ((CLIDR & 0x7) == 0x4) {

+    // Unified cache

+    return TRUE;

+  }

+  

+  return FALSE;

+}

+  

+UINTN

+EFIAPI

+ArmInstructionCacheSize (

+  VOID

+  )

+{

+  UINT32 NumSets;

+  UINT32 Associativity;

+  UINT32 LineSize;

+  UINT32 CCSIDR = ReadCCSIDR (1);

+  

+  LineSize      = (1 << ((CCSIDR & 0x7) + 2));

+  Associativity = ((CCSIDR >> 3) & 0x3ff) + 1;

+  NumSets       = ((CCSIDR >> 13) & 0x7fff) + 1;

+

+  // LineSize is in words (4 byte chunks)

+  return  NumSets * Associativity * LineSize * 4;      

+}

+  

+UINTN

+EFIAPI

+ArmInstructionCacheAssociativity (

+  VOID

+  )

+{

+  UINT32 CCSIDR = ReadCCSIDR (1);

+

+  return ((CCSIDR >> 3) & 0x3ff) + 1;

+//  return 4;

+}

+  

+UINTN

+EFIAPI

+ArmInstructionCacheSets (

+  VOID

+  )

+{

+  UINT32 CCSIDR = ReadCCSIDR (1);

+  

+  return ((CCSIDR >> 13) & 0x7fff) + 1;

+}

+

+UINTN

+EFIAPI

+ArmInstructionCacheLineLength (

+  VOID

+  )

+{

+  UINT32 CCSIDR = ReadCCSIDR (1) & 7;

+

+  // * 4 converts to bytes

+  return (1 << (CCSIDR + 2)) * 4;

+

+//  return 64;

+}

+

+

+VOID

+ArmV7DataCacheOperation (

+  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation

+  )

+{

+  UINTN     SavedInterruptState;

+

+  SavedInterruptState = ArmGetInterruptState ();

+  ArmDisableInterrupts ();

+  

+  ArmV7AllDataCachesOperation (DataCacheOperation);

+  

+  ArmDrainWriteBuffer ();

+  

+  if (SavedInterruptState) {

+    ArmEnableInterrupts ();

+  }

+}

+

+

+VOID

+ArmV7PoUDataCacheOperation (

+  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation

+  )

+{

+  UINTN     SavedInterruptState;

+

+  SavedInterruptState = ArmGetInterruptState ();

+  ArmDisableInterrupts ();

+  

+  ArmV7PerformPoUDataCacheOperation (DataCacheOperation);

+  

+  ArmDrainWriteBuffer ();

+  

+  if (SavedInterruptState) {

+    ArmEnableInterrupts ();

+  }

+}

+

+VOID

+EFIAPI

+ArmInvalidateDataCache (

+  VOID

+  )

+{

+  ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);

+}

+

+VOID

+EFIAPI

+ArmCleanInvalidateDataCache (

+  VOID

+  )

+{

+  ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);

+}

+

+VOID

+EFIAPI

+ArmCleanDataCache (

+  VOID

+  )

+{

+  ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);

+}

+

+VOID

+EFIAPI

+ArmCleanDataCacheToPoU (

+  VOID

+  )

+{

+  ArmV7PoUDataCacheOperation (ArmCleanDataCacheEntryBySetWay);

+}