diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-09 13:27:15 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-09 13:27:15 +0000 |
| commit | c722289324223c472fcf920f860dc4b49314dedf (patch) | |
| tree | 7a59af5936ffd8ac8f6779f653562cb278b10131 /ArmPkg/Library/ArmLib/ArmV7 | |
| parent | fbf658ebc8e2e9340b036b16f2c94403696df1c0 (diff) | |
| download | edk2-c722289324223c472fcf920f860dc4b49314dedf.tar.gz edk2-c722289324223c472fcf920f860dc4b49314dedf.tar.bz2 edk2-c722289324223c472fcf920f860dc4b49314dedf.zip | |
ArmPkg/ArmLib: move cache maintenance sync barriers out of loop
There is no need to issue a full data synchronization barrier and an
instruction synchronization barrier after each and every set/way or
MVA cache maintenance operation. For the set/way case, we can simply
remove them, since the set/way outer loop already issues the required
barriers after completing its traversal over all the cache levels.
For the MVA case, move the data synchronization barrier out of the
loop, and add the instruction synchronization barrier to the I-cache
invalidation by MVA routine.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18755 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Library/ArmLib/ArmV7')
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S | 12 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm | 12 |
2 files changed, 0 insertions, 24 deletions
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S index fdc4d03776..93164b8f0e 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S @@ -62,42 +62,30 @@ GCC_ASM_EXPORT (ArmReadIdPfr1) ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
- dsb
- isb
bx lr
ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
- dsb
- isb
bx lr
ASM_PFX(ArmCleanDataCacheEntryBySetWay):
mcr p15, 0, r0, c7, c10, 2 @ Clean this line
- dsb
- isb
bx lr
ASM_PFX(ArmInvalidateInstructionCache):
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm index f16dd4a4ab..d6f249038a 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm @@ -62,42 +62,30 @@ CTRL_I_BIT EQU (1 << 12) ArmInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
- dsb
- isb
bx lr
ArmCleanDataCacheEntryByMVA
mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
- dsb
- isb
bx lr
ArmCleanInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
- dsb
- isb
bx lr
ArmInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
- dsb
- isb
bx lr
ArmCleanInvalidateDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
- dsb
- isb
bx lr
ArmCleanDataCacheEntryBySetWay
mcr p15, 0, r0, c7, c10, 2 ; Clean this line
- dsb
- isb
bx lr
|