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authorAshish Singhal <ashishsingha@nvidia.com>2020-03-19 10:37:05 -0600
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2020-03-19 17:35:32 +0000
commit0c8ea9fe1adbbee230ee0c68f28b68ca2b0534bc (patch)
tree9a740c74021fb8b3f16c10c90096fc301e662a16 /ArmPkg/Library
parent1b6b4a83e1d85e48837068dfe409f5557b50d71d (diff)
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ArmPkg/ArmLib: Fix cache-invalidate initial page tables
Because of a bug, current EL gets passed to DC IVAC instruction instead of the VA entry that needs to be invalidated. Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Diffstat (limited to 'ArmPkg/Library')
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
index f744cd6738..ba0ec5682b 100644
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S
@@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR)
ASM_FUNC(ArmUpdateTranslationTableEntry)
dsb nshst
lsr x1, x1, #12
- EL1_OR_EL2_OR_EL3(x0)
+ EL1_OR_EL2_OR_EL3(x2)
1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
mrs x2, sctlr_el1
b 4f