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| author | Olivier Martin <olivier.martin@arm.com> | 2013-10-24 11:49:32 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2013-10-24 11:49:32 +0000 |
| commit | eb5c268fb6a729ab3730d0ab510564302b681490 (patch) | |
| tree | d00fc9d34cfd46e497621c4a7d6224a8bc4ae57e /ArmPkg | |
| parent | d62f9aa6e6f575a6350bb2dad89545b2430a6762 (diff) | |
| download | edk2-eb5c268fb6a729ab3730d0ab510564302b681490.tar.gz edk2-eb5c268fb6a729ab3730d0ab510564302b681490.tar.bz2 edk2-eb5c268fb6a729ab3730d0ab510564302b681490.zip | |
ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers when Uniprocessor
When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero).
So the previous assertion was not correct.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Drivers/PL390Gic/PL390GicDxe.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c index ce96831a42..111ce14438 100644 --- a/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c +++ b/ArmPkg/Drivers/PL390Gic/PL390GicDxe.c @@ -378,12 +378,12 @@ InterruptDxeInitialize ( CpuTarget = MmioRead32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR);
// The CPU target is a bit field mapping each CPU to a GIC CPU Interface. This value
- // cannot be 0.
- ASSERT (CpuTarget != 0);
-
- // The 8 first Interrupt Processor Targets Registers are read-only
- for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
- MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
+ // is 0 when we run on a uniprocessor platform.
+ if (CpuTarget != 0) {
+ // The 8 first Interrupt Processor Targets Registers are read-only
+ for (Index = 8; Index < (mGicNumInterrupts / 4); Index++) {
+ MmioWrite32 (PcdGet32 (PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index * 4), CpuTarget);
+ }
}
// Set binary point reg to 0x7 (no preemption)
|