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authorEugene Cohen <eugene@hp.com>2015-12-08 15:58:53 +0000
committerabiesheuvel <abiesheuvel@Edk2>2015-12-08 15:58:53 +0000
commitb7de7e3cab3f172bb8ef3e2638f90889981d791a (patch)
tree72f1cff046f798823c956cde71870b60b900a78b /ArmPkg
parent62c12ff8c7e7c34af2724758e49b35c26897f2d8 (diff)
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ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU
This patch updates the ArmPkg variant of InvalidateInstructionCacheRange to flush the data cache only to the point of unification (PoU). This improves performance and also allows invalidation in scenarios where it would be inappropriate to flush to the point of coherency (like when executing code from L2 configured as cache-as-ram). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Added AARCH64 and ARM/GCC implementations of the above. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@19174 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
-rw-r--r--ArmPkg/Include/Library/ArmLib.h8
-rw-r--r--ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c2
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/AArch64Support.S6
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S6
-rw-r--r--ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm5
5 files changed, 25 insertions, 2 deletions
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 9622444ec6..85fa1f600b 100644
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -183,12 +183,18 @@ ArmInvalidateDataCacheEntryByMVA (
VOID
EFIAPI
-ArmCleanDataCacheEntryByMVA (
+ArmCleanDataCacheEntryToPoUByMVA(
IN UINTN Address
);
VOID
EFIAPI
+ArmCleanDataCacheEntryByMVA(
+IN UINTN Address
+);
+
+VOID
+EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
IN UINTN Address
);
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
index feab4497ac..1045f9068f 100644
--- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
+++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
@@ -64,7 +64,7 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
- CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);
+ CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA);
ArmInvalidateInstructionCache ();
return Address;
}
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index c530d19e89..db21f73f0e 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -22,6 +22,7 @@
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
@@ -72,6 +73,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA):
ret
+ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
+ dc cvau, x0 // Clean single data cache line to PoU
+ ret
+
+
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
dc civac, x0 // Clean and invalidate single data cache line
ret
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
index 5f030d92de..7de1b11ef8 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
@@ -19,6 +19,7 @@
GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
+GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
@@ -69,6 +70,11 @@ ASM_PFX(ArmCleanDataCacheEntryByMVA):
bx lr
+ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
+ mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
+ bx lr
+
+
ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
bx lr
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
index df7e22dca2..a460bd2da7 100644
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
@@ -34,6 +34,11 @@ CTRL_I_BIT EQU (1 << 12)
bx lr
+ RVCT_ASM_EXPORT ArmCleanDataCacheEntryToPoUByMVA
+ mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU
+ bx lr
+
+
RVCT_ASM_EXPORT ArmCleanInvalidateDataCacheEntryByMVA
mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
bx lr