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| author | Rebecca Cran <quic_rcran@quicinc.com> | 2023-01-16 21:57:30 -0700 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-01-27 14:18:56 +0000 |
| commit | d1855afc6e0ef37eeaef1c8c10aff55b1c9995b9 (patch) | |
| tree | 54395c49a6e9bfcec0e1bfd7a0d247f94a044414 /ArmPkg | |
| parent | 0d129ef7c3a95d64f2f2cab4f8302318775f9933 (diff) | |
| download | edk2-d1855afc6e0ef37eeaef1c8c10aff55b1c9995b9.tar.gz edk2-d1855afc6e0ef37eeaef1c8c10aff55b1c9995b9.tar.bz2 edk2-d1855afc6e0ef37eeaef1c8c10aff55b1c9995b9.zip | |
ArmPkg: Add GET_MPIDR_AFFINITY_BITS and MPIDR_MT_BIT to ArmLib.h
Signed-off-by: Rebecca Cran <rebecca@quicinc.com>
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Include/Library/ArmLib.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 6566deebdd..fa605f128b 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -108,14 +108,16 @@ typedef enum { #define ARM_CORE_MASK ARM_CORE_AFF0
#define ARM_CLUSTER_MASK ARM_CORE_AFF1
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
-#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
-#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
-#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
-#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+#define GET_MPIDR_AFF0(MpId) ((MpId) & ARM_CORE_AFF0)
+#define GET_MPIDR_AFF1(MpId) (((MpId) & ARM_CORE_AFF1) >> 8)
+#define GET_MPIDR_AFF2(MpId) (((MpId) & ARM_CORE_AFF2) >> 16)
+#define GET_MPIDR_AFF3(MpId) (((MpId) & ARM_CORE_AFF3) >> 32)
+#define GET_MPIDR_AFFINITY_BITS(MpId) ((MpId) & 0xFF00FFFFFF)
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
+#define MPIDR_MT_BIT BIT24
/** Reads the CCSIDR register for the specified cache.
|