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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-18 15:59:04 +0000 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-18 15:59:04 +0000 |
| commit | 07070ecc76cff00175715f9a9534bc9216599a11 (patch) | |
| tree | 2bb576b33b75c70f5db5a7110cff964c3315c7ce /ArmPkg | |
| parent | 2ea66ed9f9ea18cbe2681baaad29ce47ea9918a1 (diff) | |
| download | edk2-07070ecc76cff00175715f9a9534bc9216599a11.tar.gz edk2-07070ecc76cff00175715f9a9534bc9216599a11.tar.bz2 edk2-07070ecc76cff00175715f9a9534bc9216599a11.zip | |
ArmPkg/ArmV7Mmu: make cached translation table accesses shareable
To align with the way normal cacheable memory is mapped, set the
shareable bit for cached accesses performed by the page table walker.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
| -rw-r--r-- | ArmPkg/Include/Chipset/ArmV7Mmu.h | 6 | ||||
| -rw-r--r-- | ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c | 13 |
2 files changed, 16 insertions, 3 deletions
diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h index 2545864775..f612154bad 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -29,10 +29,10 @@ #define TTBR_RGN_INNER_WRITE_THROUGH BIT0
#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
-#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH )
-#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC )
+#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
+#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
-#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC )
+#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
#define TRANSLATION_TABLE_SECTION_COUNT 4096
diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c index 8ed763cc82..f03f609d21 100644 --- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c +++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c @@ -265,6 +265,19 @@ ArmConfigureMmu ( return RETURN_UNSUPPORTED;
}
+ if (TTBRAttributes & TTBR_SHAREABLE) {
+ //
+ // Unlike the S bit in the short descriptors, which implies inner shareable
+ // on an implementation that supports two levels, the meaning of the S bit
+ // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.
+ // However, we should only set this bit after we have confirmed that the
+ // implementation supports multiple levels, or else the NOS bit is UNK/SBZP
+ //
+ if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {
+ TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;
+ }
+ }
+
ArmCleanInvalidateDataCache ();
ArmInvalidateInstructionCache ();
|