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authorMark Rutland <mark.rutland@arm.com>2015-11-09 13:25:12 +0000
committerabiesheuvel <abiesheuvel@Edk2>2015-11-09 13:25:12 +0000
commitee95f9e1faf0158db6ba517ab500779242b68163 (patch)
tree919cee89dc2b6befc6ddfaff258f649ff9286bfa /ArmPkg
parentf3e88737f78135f70a5bb79283e40b829bdb02dd (diff)
downloadedk2-ee95f9e1faf0158db6ba517ab500779242b68163.tar.gz
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ArmPkg/ArmLib: fix barriers in AArch64 ArmEnableMmu
The ARM architecture requires a DSB to complete TLB maintenance, with a subsequent ISB being required to synchronize subsequent items in the current instruction stream against the completed TLB maintenance. The ArmEnableMmu function is currently missing the DSB, and hence the TLB maintenance is not guaranteed to have completed at the point the MMU is enabled. This may result in unpredictable behaviour. The DSB subsequent to the write to SCTLR_EL1 is unnecessary; the ISB alone is sufficient to complete all prior instructions and to synchronise the new context with any subsequent instructions. This patch adds missing DSBs to complete TLB maintenance, and removes the unnecessary trailing DSB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18749 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg')
-rw-r--r--ArmPkg/Library/ArmLib/AArch64/AArch64Support.S6
1 files changed, 4 insertions, 2 deletions
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index bdede48724..28cf27fbd1 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -123,18 +123,20 @@ ASM_PFX(ArmEnableMmu):
4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
EL1_OR_EL2_OR_EL3(x1)
1: tlbi vmalle1
+ dsb nsh
isb
msr sctlr_el1, x0 // Write back
b 4f
2: tlbi alle2
+ dsb nsh
isb
msr sctlr_el2, x0 // Write back
b 4f
3: tlbi alle3
+ dsb nsh
isb
msr sctlr_el3, x0 // Write back
-4: dsb sy
- isb
+4: isb
ret