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| author | Leendert van Doorn <leendert@paramecium.org> | 2016-03-24 15:30:08 -0500 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2016-03-25 07:17:28 +0100 |
| commit | 91673dfdfe78906023f07e585002689e8baf654e (patch) | |
| tree | 9e312d40a4e42f84df1e612653afe4c8735c7308 /ArmPlatformPkg/ArmPlatformPkg.dec | |
| parent | 7e5a6e394c65a295a761162621c546b1fea0b280 (diff) | |
| download | edk2-91673dfdfe78906023f07e585002689e8baf654e.tar.gz edk2-91673dfdfe78906023f07e585002689e8baf654e.tar.bz2 edk2-91673dfdfe78906023f07e585002689e8baf654e.zip | |
ArmPlatformPkg: fixups for 64-bit pointers
This retypes some stack base PCD as 64-bit, and fixes up a number of references
to 64-bit PCDs (including the retypes ones), to use the correct PcdGet64()
accessors. Note that, in the case of FixedPcdGet64, this does not actually
caused any problems, since that resolves to an immediate value. But the
generic PcdGetxx accessors should be typed according to the size of the PCD.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
[ard.biesheuvel: fixed up some instances in the 32-bit ARM code]
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'ArmPlatformPkg/ArmPlatformPkg.dec')
| -rw-r--r-- | ArmPlatformPkg/ArmPlatformPkg.dec | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index e881c13439..2d06275953 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -62,7 +62,7 @@ gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
# Stack for CPU Cores in Secure Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
@@ -188,13 +188,13 @@ [PcdsFixedAtBuild.ARM]
# Stack for CPU Cores in Secure Monitor Mode
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
[PcdsFixedAtBuild.AARCH64]
# The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
# The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
# and PcdCPUCoreSecSecondaryStackSize
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
|