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| author | Laszlo Ersek <lersek@redhat.com> | 2015-02-23 16:02:44 +0000 |
|---|---|---|
| committer | lersek <lersek@Edk2> | 2015-02-23 16:02:44 +0000 |
| commit | e48f1f15b0e2947a49a3945d6b6813e33e137adb (patch) | |
| tree | 2931e1ba28f7939e1dc4bfce8084a2d54aeba955 /ArmPlatformPkg/ArmPlatformPkg.dec | |
| parent | 93deff5aca6e0ad03e55d6276e81a6d8efb134b1 (diff) | |
| download | edk2-e48f1f15b0e2947a49a3945d6b6813e33e137adb.tar.gz edk2-e48f1f15b0e2947a49a3945d6b6813e33e137adb.tar.bz2 edk2-e48f1f15b0e2947a49a3945d6b6813e33e137adb.zip | |
ArmPlatformPkg: introduce PCDs for describing PCI address spaces
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16893 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg/ArmPlatformPkg.dec')
| -rw-r--r-- | ArmPlatformPkg/ArmPlatformPkg.dec | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec b/ArmPlatformPkg/ArmPlatformPkg.dec index 57a43c5037..2515af8e59 100644 --- a/ArmPlatformPkg/ArmPlatformPkg.dec +++ b/ArmPlatformPkg/ArmPlatformPkg.dec @@ -152,6 +152,68 @@ gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
+ #
+ # Inclusive range of allowed PCI buses.
+ #
+ gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
+ gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
+
+ #
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
+ # Note that "IO" is just another MMIO range that simulates IO space; there
+ # are no special instructions to access it.
+ #
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
+ # specific to their containing address spaces. In order to get the physical
+ # address for the CPU, for a given access, the respective translation value
+ # has to be added.
+ #
+ # The translations always have to be initialized like this, using UINT64:
+ #
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
+ #
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
+ #
+ # because (a) the target address space (ie. the cpu-physical space) is
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*
+ # arithmetic.
+ #
+ # Accordingly, the translation itself needs to be implemented as:
+ #
+ # UINT64 UntranslatedIoAddress; // input parameter
+ # UINT32 UntranslatedMmio32Address; // input parameter
+ # UINT64 UntranslatedMmio64Address; // input parameter
+ #
+ # UINT64 TranslatedIoAddress; // output parameter
+ # UINT64 TranslatedMmio32Address; // output parameter
+ # UINT64 TranslatedMmio64Address; // output parameter
+ #
+ # TranslatedIoAddress = UntranslatedIoAddress +
+ # PcdPciIoTranslation;
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
+ # PcdPciMmio32Translation;
+ # TranslatedMmio64Address = UntranslatedMmio64Address +
+ # PcdPciMmio64Translation;
+ #
+ # The modular arithmetic performed in UINT64 ensures that the translation
+ # works correctly regardless of the relation between IoCpuBase and
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
+ # PcdPciMmio64Base.
+ #
+ gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
+ gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
+ gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
+ gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
+ gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
+
[PcdsFixedAtBuild.ARM]
# Stack for CPU Cores in Secure Monitor Mode
gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
|