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authoroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2013-03-12 00:45:29 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2013-03-12 00:45:29 +0000
commit6f711615bacf7ce3bc42507cba87bc0adcda0461 (patch)
treed0e44d445e1add7054335d5a4c826dcfb888cee7 /ArmPlatformPkg
parent8274521330e956ada5b9fc2a21aa81bd9d872f4c (diff)
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ARM Packages: Fixed coding style and typos
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14179 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg')
-rw-r--r--ArmPlatformPkg/PrePeiCore/MainMPCore.c4
-rw-r--r--ArmPlatformPkg/Sec/Sec.c10
2 files changed, 7 insertions, 7 deletions
diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
index aeea8f5bda..afe36a7538 100644
--- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c
+++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c
@@ -121,7 +121,7 @@ PrimaryMain (
CreatePpiList (&PpiListSize, &PpiList);
// Enable the GIC Distributor
- ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores
if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {
@@ -155,5 +155,5 @@ PrimaryMain (
SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;
// Jump to PEI core entry point
- (PeiCoreEntryPoint)(&SecCoreData, PpiList);
+ PeiCoreEntryPoint (&SecCoreData, PpiList);
}
diff --git a/ArmPlatformPkg/Sec/Sec.c b/ArmPlatformPkg/Sec/Sec.c
index be165442bf..52fa53a647 100644
--- a/ArmPlatformPkg/Sec/Sec.c
+++ b/ArmPlatformPkg/Sec/Sec.c
@@ -35,20 +35,20 @@ CEntryPoint (
UINTN JumpAddress;
// Invalidate the data cache. Doesn't have to do the Data cache clean.
- ArmInvalidateDataCache();
+ ArmInvalidateDataCache ();
// Invalidate Instruction Cache
- ArmInvalidateInstructionCache();
+ ArmInvalidateInstructionCache ();
// Invalidate I & D TLBs
- ArmInvalidateInstructionAndDataTlb();
+ ArmInvalidateInstructionAndDataTlb ();
// CPU specific settings
ArmCpuSetup (MpId);
// Enable Floating Point Coprocessor if supported by the platform
if (FixedPcdGet32 (PcdVFPEnabled)) {
- ArmEnableVFP();
+ ArmEnableVFP ();
}
// Initialize peripherals that must be done at the early stage
@@ -95,7 +95,7 @@ CEntryPoint (
// Test if Trustzone is supported on this platform
if (FixedPcdGetBool (PcdTrustzoneSupport)) {
- if (ArmIsMpCore()) {
+ if (ArmIsMpCore ()) {
// Setup SMP in Non Secure world
ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
}