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authorBrendan Jackman <brendan.jackman@arm.com>2014-05-08 14:59:04 +0000
committeroliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524>2014-05-08 14:59:04 +0000
commit73ca50096eea3edc64e2c635b6b6d99fbb5572d5 (patch)
treec2005188cc6c82478ff1a1e0e3c101297e64d53e /ArmPlatformPkg
parent7eb1d8522a583b2a0a8eea5034be7b30ab14e0f8 (diff)
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ARM Packages: Use AND instead of BIC instruction with immediate
AARCH64 does not have a BIC-with-immediate instruction. GAS assembles it as a AND with the immediate inverted, but Clang's integrated assembler emits an error. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15509 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPlatformPkg')
-rw-r--r--ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S3
-rw-r--r--ArmPlatformPkg/Sec/AArch64/Helper.S6
2 files changed, 4 insertions, 5 deletions
diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S
index 7d9c25c769..035e095493 100644
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S
@@ -12,6 +12,7 @@
//
#include <AsmMacroIoLibV8.h>
+#include <Chipset/AArch64.h>
#ifndef __clang__
// Register definitions used by GCC for GICv3 access.
@@ -64,6 +65,6 @@ ASM_PFX(InitializeGicV3):
// Remove the SCR.NS bit
mrs x0, scr_el3
- bic x0, x0, #1
+ and x0, x0, #~SCR_NS
msr scr_el3, x0
ret
diff --git a/ArmPlatformPkg/Sec/AArch64/Helper.S b/ArmPlatformPkg/Sec/AArch64/Helper.S
index 259aca4856..3b58e12292 100644
--- a/ArmPlatformPkg/Sec/AArch64/Helper.S
+++ b/ArmPlatformPkg/Sec/AArch64/Helper.S
@@ -1,5 +1,5 @@
#========================================================================================
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
@@ -31,9 +31,7 @@ ASM_PFX(SwitchToNSExceptionLevel1):
orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
// Send all interrupts to their respective Exception levels for EL2
- bic x0, x0, #(1 << 3) // Disable virtual FIQ
- bic x0, x0, #(1 << 4) // Disable virtual IRQ
- bic x0, x0, #(1 << 5) // Disable virtual SError and Abort
+ and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort
msr hcr_el2, x0 // Write back our settings
msr cptr_el2, xzr // Disable copro traps to EL2