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| author | Eric Dong <eric.dong@intel.com> | 2018-09-25 08:32:31 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2018-09-26 15:17:15 +0800 |
| commit | 4382394aa96b6d86ee9c2d6a7b8db674cc78b148 (patch) | |
| tree | 6b36b864d56ad6e83e2dd84f48fa5a106a1c84e2 /BaseTools/Source/Python/AutoGen/BuildEngine.py | |
| parent | 140d713175f8a6176e67f179fc31b540461d81e5 (diff) | |
| download | edk2-4382394aa96b6d86ee9c2d6a7b8db674cc78b148.tar.gz edk2-4382394aa96b6d86ee9c2d6a7b8db674cc78b148.tar.bz2 edk2-4382394aa96b6d86ee9c2d6a7b8db674cc78b148.zip | |
UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.
V3 changes include:
1. Keep ReservedX not change if bit info not changed for this field.
V2 changes include:
1. Use X in ReservedX fields from totally new value if MSR structure definition changed.
For example, if in current structure, the max reserved variable is Reserved2, in new
definition, reserved variable is begin with Reserved3.
V1 Changes includes:
1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/BuildEngine.py')
0 files changed, 0 insertions, 0 deletions