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| author | Ni, Ray <ray.ni@intel.com> | 2019-08-01 17:58:29 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2019-08-09 08:52:09 +0800 |
| commit | b3527dedc3951f061c5a73cb4fb2b0f95f47e08b (patch) | |
| tree | 4a71ebd702bf63e00c4fdf9ca411f4115bf37cfd /BaseTools/Source/Python/AutoGen/BuildEngine.py | |
| parent | 236d5c66c4e14960e54c33838b53130560b6e867 (diff) | |
| download | edk2-b3527dedc3951f061c5a73cb4fb2b0f95f47e08b.tar.gz edk2-b3527dedc3951f061c5a73cb4fb2b0f95f47e08b.tar.bz2 edk2-b3527dedc3951f061c5a73cb4fb2b0f95f47e08b.zip | |
MdeModulePkg/DxeIpl: Create 5-level page table for long mode
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008
DxeIpl is responsible to create page table for DXE phase running
either in long mode or in 32bit mode with certain protection
mechanism enabled (refer to ToBuildPageTable()).
The patch updates DxeIpl to create 5-level page table for DXE phase
running in long mode when PcdUse5LevelPageTable is TRUE and CPU
supports 5-level page table.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/BuildEngine.py')
0 files changed, 0 insertions, 0 deletions