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| author | Sunil V L <sunilvl@ventanamicro.com> | 2021-06-24 21:25:31 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-06-29 02:47:44 +0000 |
| commit | abfff7c45d43360ebd292dc26b6542094c145f5f (patch) | |
| tree | 6e04bf9ace24f0f239a64560530027e599ab4d9b /BaseTools/Source/Python/AutoGen/DataPipe.py | |
| parent | 17143c4837393d42c484b42d1789b85b2cff1aaf (diff) | |
| download | edk2-abfff7c45d43360ebd292dc26b6542094c145f5f.tar.gz edk2-abfff7c45d43360ebd292dc26b6542094c145f5f.tar.bz2 edk2-abfff7c45d43360ebd292dc26b6542094c145f5f.zip | |
BaseTools GenFw: Add support for RISCV GOT/PLT relocations
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096
This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710
Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/DataPipe.py')
0 files changed, 0 insertions, 0 deletions