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| author | Star Zeng <star.zeng@intel.com> | 2018-10-22 16:29:03 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-10-28 21:20:06 +0800 |
| commit | 6681582dcce3a08ce3cb3042b2f4a09e9d3c9d72 (patch) | |
| tree | 793e95a59c9e80abdb18fdcd466647b078fd6270 /BaseTools/Source/Python/AutoGen/GenMake.py | |
| parent | a6eb94eedb32b79e8721caa6c98ce898b4b7170c (diff) | |
| download | edk2-6681582dcce3a08ce3cb3042b2f4a09e9d3c9d72.tar.gz edk2-6681582dcce3a08ce3cb3042b2f4a09e9d3c9d72.tar.bz2 edk2-6681582dcce3a08ce3cb3042b2f4a09e9d3c9d72.zip | |
MdeModulePkg XhciDxe: Extract new XhciInsertAsyncIntTransfer function
V3:
Match function parameter name and description between
XhciSched.c and XhciSched.h.
V2:
Add the missing "FreePool (Data);".
Remove the unnecessary indentation change.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1274
Extract new XhciInsertAsyncIntTransfer function from
XhcAsyncInterruptTransfer.
It is code preparation for following patch,
no essential functional change.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/GenMake.py')
0 files changed, 0 insertions, 0 deletions