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| author | Star Zeng <star.zeng@intel.com> | 2018-03-28 16:52:12 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-05-09 16:27:30 +0800 |
| commit | e91797885aee58ae65d7935332e580dc8517e8f6 (patch) | |
| tree | 482e631d32f1b3196949de9dae201e6b83e4ff05 /BaseTools/Source/Python/AutoGen/GenMake.py | |
| parent | 0edb7ec5ced0a28b93bf8c13b12f0a277c44dbbc (diff) | |
| download | edk2-e91797885aee58ae65d7935332e580dc8517e8f6.tar.gz edk2-e91797885aee58ae65d7935332e580dc8517e8f6.tar.bz2 edk2-e91797885aee58ae65d7935332e580dc8517e8f6.zip | |
IntelSiliconPkg MicrocodeUpdateDxe: Honor FIT table
It is the second step for
https://bugzilla.tianocore.org/show_bug.cgi?id=540.
V2: Use error handling instead of ASSERT for FIT table checking result.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/GenMake.py')
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