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| author | Ray Ni <ray.ni@intel.com> | 2019-06-12 11:04:52 +0800 |
|---|---|---|
| committer | Ray Ni <ray.ni@intel.com> | 2019-07-12 15:12:43 +0800 |
| commit | 6e5a33d1fba7c170dc8680eeb81a9c7f4fe14fe6 (patch) | |
| tree | 147812ab903aede3c18798c2d7223cc0841285c1 /BaseTools/Source/Python/AutoGen/GenVar.py | |
| parent | deb90ac03a0416d370975d8bada28620fda0ea87 (diff) | |
| download | edk2-6e5a33d1fba7c170dc8680eeb81a9c7f4fe14fe6.tar.gz edk2-6e5a33d1fba7c170dc8680eeb81a9c7f4fe14fe6.tar.bz2 edk2-6e5a33d1fba7c170dc8680eeb81a9c7f4fe14fe6.zip | |
MdePkg/BaseLib.h: Update IA32_CR4 structure for 5-level paging
5-level paging is documented in white paper:
https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf
Commit f8113e25001e715390127f23e2197252cbd6d1a2
changed Cpuid.h already.
This patch updates IA32_CR4 structure to include LA57 field.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
(cherry picked from commit 7c5010c7f88b790f4524c4a5311819e3af5e2752)
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/GenVar.py')
0 files changed, 0 insertions, 0 deletions