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| author | Albecki, Mateusz </o=Intel/ou=Exchange Administrative Group (FYDIBOHF23SPDLT)/cn=Recipients/cn=Albecki, Mateusz3be> | 2019-02-18 19:11:37 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2019-02-20 09:07:17 +0800 |
| commit | 195f673f6270aaf73dd34b75f1da26451b63c316 (patch) | |
| tree | 055bc0edc31e7f9a462dbb3bc3d58b6c74d8e4fc /BaseTools/Source/Python/AutoGen/IdfClassObject.py | |
| parent | 68c67d3a2a33261e41ff0123129b4e9759617f71 (diff) | |
| download | edk2-195f673f6270aaf73dd34b75f1da26451b63c316.tar.gz edk2-195f673f6270aaf73dd34b75f1da26451b63c316.tar.bz2 edk2-195f673f6270aaf73dd34b75f1da26451b63c316.zip | |
MdeModulePkg/SdMmcPciHcDxe Fix eMMC HS400 switch sequence
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1140
In eMMC HS400 switch sequence flow eMMC driver attempted
to execute SEND_STATUS just after switching bus timing to high
speed and before downgrading clock frequency to 52MHz. Since link
was at that time in incorrect state SEND_STATUS was failing which
made driver think switch to HS400 failed.
This change makes driver always change clock frequency after
switching bus timing and before executing SEND_STATUS.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Albecki Mateusz <mateusz.albecki@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/AutoGen/IdfClassObject.py')
0 files changed, 0 insertions, 0 deletions