UefiCpuPkg/S3Resume2Pei: disable paging before creating new page table.

V5:
1. Add ASSERT to indicate this assumption that environment is 32 bit mode.
2. Add description in INF about this driver's expected result
   in different environment.

V4:
Only disable paging when it is enabled.

V3 changes:
No need to change inf file.

V2 changes:
Only disable paging in 32 bit mode, no matter it is enable or not.

V1 changes:
PEI Stack Guard needs to enable paging. This might cause #GP if code
trying to write CR3 register with PML4 page table while the processor
is enabled with PAE paging.

Simply disabling paging before updating CR3 can solve this conflict.

It's an regression caused by change: 0a0d5296e448fc350de1594c49b9c0deff7fad60

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1232

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>

0 files changed, 0 insertions, 0 deletions