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| author | Star Zeng <star.zeng@intel.com> | 2018-09-05 08:54:54 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-09-12 12:57:16 +0800 |
| commit | 73dbd6afab356663c86ed412a0440a96e8064dd7 (patch) | |
| tree | f1a7ca001da90386d7d6b953764dfb45c3ed0dfa /BaseTools/Source/Python/Common/EdkLogger.py | |
| parent | 84a52d4d030185a44f2d8736142c6f0b19c6e9b1 (diff) | |
| download | edk2-73dbd6afab356663c86ed412a0440a96e8064dd7.tar.gz edk2-73dbd6afab356663c86ed412a0440a96e8064dd7.tar.bz2 edk2-73dbd6afab356663c86ed412a0440a96e8064dd7.zip | |
MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1167
When the HSEE in the USBCMD bit is a ‘1’ and the HSE bit in the
USBSTS register is a ‘1’, the xHC shall assert out-of-band error
signaling to the host and assert the SERR# pin.
To prevent masking any potential issues with SERR, this patch is
to set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR#
Enable Bit is set.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Fei1 Wang <fei1.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/EdkLogger.py')
0 files changed, 0 insertions, 0 deletions