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| author | Javeed, Ashraf <ashraf.javeed@intel.com> | 2020-03-17 16:04:13 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-03-19 00:48:02 +0000 |
| commit | 1b6b4a83e1d85e48837068dfe409f5557b50d71d (patch) | |
| tree | 0353db7522e0c140a9f94e33ea9302991f0b6d69 /BaseTools/Source/Python/Common/VariableAttributes.py | |
| parent | 01ce872739d2f0cd3a8917be2180381db5f0391e (diff) | |
| download | edk2-1b6b4a83e1d85e48837068dfe409f5557b50d71d.tar.gz edk2-1b6b4a83e1d85e48837068dfe409f5557b50d71d.tar.bz2 edk2-1b6b4a83e1d85e48837068dfe409f5557b50d71d.zip | |
MdePkg/PciExpress40.h: DVSEC definition missing
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/VariableAttributes.py')
0 files changed, 0 insertions, 0 deletions