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| author | Abner Chang <abner.chang@hpe.com> | 2020-07-16 12:35:32 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-08-12 04:01:39 +0000 |
| commit | e6042aec1bc2bf3a2eaf4f2d3bfe9b90ef95948e (patch) | |
| tree | cf43c75b61bc44abfd78085f592d1e574028c3eb /BaseTools/Source/Python/Common/VpdInfoFile.py | |
| parent | a3741780fe3535e19e02efa869a7cac481891129 (diff) | |
| download | edk2-e6042aec1bc2bf3a2eaf4f2d3bfe9b90ef95948e.tar.gz edk2-e6042aec1bc2bf3a2eaf4f2d3bfe9b90ef95948e.tar.bz2 edk2-e6042aec1bc2bf3a2eaf4f2d3bfe9b90ef95948e.zip | |
BaseLib:Fix RISC-V Supervisor mode (S-Mode) trap handler reentry issue.
While RISC-V hart is trapped into S-Mode, the S-Mode interrupt
CSR (SIE) is disabled by RISC-V hart. However the (SIE) is enabled
again by RestoreTPL, this causes the second S-Mode trap is triggered
by the machine mode (M-Mode)timer interrupt redirection. The SRET
instruction clear Supervisor Previous Privilege (SPP) to zero
(User mode) in the second S-Mode interrupt according to the RISC-V
spec. Above brings hart to the user mode (U-Mode) when execute
SRET in the nested S-Mode interrupt handler because SPP is set to
User Mode in the second interrupt. Afterward, system runs in U-Mode
and any accesses to S-Mode CSR causes the invalid instruction exception.
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Acked-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/VpdInfoFile.py')
0 files changed, 0 insertions, 0 deletions