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| author | Star Zeng <star.zeng@intel.com> | 2018-10-21 11:12:01 +0800 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-10-23 11:17:32 +0800 |
| commit | 4a723d3d7fd1cbbc28c92f14361761831ad27bab (patch) | |
| tree | fcaf2f4d4d222fbc5d75fedeaa3c8cd075e0f607 /BaseTools/Source/Python/Common/caching.py | |
| parent | fed6cf25b8eefccf302f90f1fa7e54bf4a91b124 (diff) | |
| download | edk2-4a723d3d7fd1cbbc28c92f14361761831ad27bab.tar.gz edk2-4a723d3d7fd1cbbc28c92f14361761831ad27bab.tar.bz2 edk2-4a723d3d7fd1cbbc28c92f14361761831ad27bab.zip | |
MdeModulePkg Xhci: Handle value 5 in Port Speed field of PORTSC
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1267
The value 5 Port Speed field of PORTSC is new defined in
XHCI 1.1 spec November 2017.
This patch updates XhciDxe and XhciPei to handle it, otherwise
the USB 3.1 device may not be recognized with the XHCI controller
following XHCI 1.1 spec November 2017.
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Hao Wu <hao.a.wu@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/caching.py')
0 files changed, 0 insertions, 0 deletions