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| author | Bandaru, Purna Chandra Rao <Purna.Chandra.Rao.Bandaru@intel.com> | 2022-03-08 20:19:35 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-03-10 01:45:14 +0000 |
| commit | f06941cc46d002f66875b6f2f711fa3df2775da4 (patch) | |
| tree | 91d5bc5935631b3175325b74b05e57579cfedacb /BaseTools/Source/Python/Common/caching.py | |
| parent | c63ef58698da1b830d25fd7239c0f5a4e28f70e4 (diff) | |
| download | edk2-f06941cc46d002f66875b6f2f711fa3df2775da4.tar.gz edk2-f06941cc46d002f66875b6f2f711fa3df2775da4.tar.bz2 edk2-f06941cc46d002f66875b6f2f711fa3df2775da4.zip | |
MdeModulePkg: Add bRefClkFreq card attribute programming support
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3851
When the UFS card comes out of Manufacturer, bRefClkFreq attribute is set
to 1h on the UFS card as per the Manufacturer Default Value
specified by the spec JESD220*. However, depends on the UFS host system
environment, it need to be set to the correct value.
Reference Clock Frequency value
0h:19.2 MHz
1h: 26 MHz
2h: 38.4 MHz
3h: Obsolete
Others: Reserved
Cc: Wu Hao A <hao.a.wu@intel.com>
Cc: Albecki Mateusz <mateusz.albecki@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Purna Chandra Rao Bandaru <purna.chandra.rao.bandaru@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/caching.py')
0 files changed, 0 insertions, 0 deletions