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| author | Jian J Wang <jian.j.wang@intel.com> | 2018-08-23 15:58:31 +0800 |
|---|---|---|
| committer | Jian J Wang <jian.j.wang@intel.com> | 2018-09-10 09:28:26 +0800 |
| commit | 2af2988f3a0268b02d87a97d5b6d7b65b17c0b03 (patch) | |
| tree | a4968ad2c7926b6e4e679b7b94be46395aafdb01 /BaseTools/Source/Python/CommonDataClass/CommonClass.py | |
| parent | 4b2dc555d8a67e715d8fafab4c9131791d31a788 (diff) | |
| download | edk2-2af2988f3a0268b02d87a97d5b6d7b65b17c0b03.tar.gz edk2-2af2988f3a0268b02d87a97d5b6d7b65b17c0b03.tar.bz2 edk2-2af2988f3a0268b02d87a97d5b6d7b65b17c0b03.zip | |
MdeModulePkg/DxeIpl: disable paging before creating new page table
PEI Stack Guard needs to enable paging before DxeIpl. This might cause
#GP in the transition from 32-bit PEI to 64-bit DXE due to the code
trying to write CR3 register with PML4 page table while the processor
is enabled with PAE paging.
Simply disabling paging before updating CR3 can solve this conflict.
There's no such issue for 64-bit PEI so this change applies only to
32-bit code.
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: "Ware, Ryan R" <ryan.r.ware@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/CommonDataClass/CommonClass.py')
0 files changed, 0 insertions, 0 deletions