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| author | Ray Ni <ray.ni@intel.com> | 2019-09-06 06:18:47 +0800 |
|---|---|---|
| committer | Ray Ni <ray.ni@intel.com> | 2019-09-13 16:20:54 +0800 |
| commit | 86ad762fa7a51cbf94e34e732961aae3de3339c3 (patch) | |
| tree | d7572c31274c1c4170de2774b73488b9adde029d /BaseTools/Source/Python/CommonDataClass/DataClass.py | |
| parent | 5a9db858806912ebd4e836aaa607ef6d87ce9c0d (diff) | |
| download | edk2-86ad762fa7a51cbf94e34e732961aae3de3339c3.tar.gz edk2-86ad762fa7a51cbf94e34e732961aae3de3339c3.tar.bz2 edk2-86ad762fa7a51cbf94e34e732961aae3de3339c3.zip | |
UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48
Today's behavior is to enable 5l paging when CPU supports it
(CPUID[7,0].ECX.BIT[16] is set).
The patch changes the behavior to enable 5l paging when two
conditions are both met:
1. CPU supports it;
2. The max physical address bits is bigger than 48.
Because 4-level paging can support to address physical address up to
2^48 - 1, there is no need to enable 5-level paging with max
physical address bits <= 48.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'BaseTools/Source/Python/CommonDataClass/DataClass.py')
0 files changed, 0 insertions, 0 deletions