diff options
| author | Eric Dong <eric.dong@intel.com> | 2018-08-30 14:04:38 +0800 |
|---|---|---|
| committer | Eric Dong <eric.dong@intel.com> | 2018-09-26 15:17:12 +0800 |
| commit | dfb208511e5770d6d0947fb9d6faa1d52a81cc9a (patch) | |
| tree | f9ab6576def4c1d8a65ceac39471272b8a54a08a /BaseTools/Source/Python/CommonDataClass/DataClass.py | |
| parent | c4b073632d6fa2fd9079fb6d088738bb7d5c7f71 (diff) | |
| download | edk2-dfb208511e5770d6d0947fb9d6faa1d52a81cc9a.tar.gz edk2-dfb208511e5770d6d0947fb9d6faa1d52a81cc9a.tar.bz2 edk2-dfb208511e5770d6d0947fb9d6faa1d52a81cc9a.zip | |
UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h: Add new MSR.
Changes includes:
1. Add new MSR definition:
1. MSR_XEON_PHI_PPIN_CTL
2. MSR_XEON_PHI_PPIN
3. MSR_XEON_PHI_MISC_FEATURE_ENABLES
4. MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT
2. Add DisplayModule == 0x85 supports.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'BaseTools/Source/Python/CommonDataClass/DataClass.py')
0 files changed, 0 insertions, 0 deletions