diff options
author | John E Lofgren <john.e.lofgren@intel.com> | 2019-09-18 23:43:23 +0800 |
---|---|---|
committer | Eric Dong <eric.dong@intel.com> | 2019-09-20 14:37:42 +0800 |
commit | f4c898f2b2db2819c519cdce05403d4ba0234979 (patch) | |
tree | 905d76e2b0bad108897e587908127350e451e594 /BaseTools/Source/Python/CommonDataClass/Exceptions.py | |
parent | 832c4c7ad6109847b2e7fdcca6bf539106523c61 (diff) | |
download | edk2-f4c898f2b2db2819c519cdce05403d4ba0234979.tar.gz edk2-f4c898f2b2db2819c519cdce05403d4ba0234979.tar.bz2 edk2-f4c898f2b2db2819c519cdce05403d4ba0234979.zip |
UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2150
v4:
The v3 posting didn't do what it promised to do, so do it now for real.
V3 changes:
change to mov instruction (non locking instuction) instead
of xchg to simplify design.
V2 changes:
Add xchg 16 bit instructions to handle sgdt and sidt base
63:48 bits and 47:32 bits.
Add comment to explain why xchg 64bit isnt being used
Split lock happens when a locking instruction is used on mis-aligned data
that crosses two cachelines. If close source platform enables Alignment
Check Exception(#AC), They can hit a double fault due to split lock being
in CpuExceptionHandlerLib.
sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limit.
The data is mis-aligned, can cross two cacheline, and a xchg
instruction(locking instuction) is being utilize.
Signed-off-by: John E Lofgren <john.e.lofgren@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Diffstat (limited to 'BaseTools/Source/Python/CommonDataClass/Exceptions.py')
0 files changed, 0 insertions, 0 deletions