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| author | Tom Lendacky <thomas.lendacky@amd.com> | 2021-01-07 12:48:19 -0600 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-01-07 19:34:39 +0000 |
| commit | 31f5ebd6db0805cdcafb1312a91b60d14ff1ac24 (patch) | |
| tree | 996d42cb4d12db9f8474ba536049ca936ea448b3 /BaseTools/Source/Python/CommonDataClass/FdfClass.py | |
| parent | 84cddd70820f35e8bd0f169078765548eab3d3ca (diff) | |
| download | edk2-31f5ebd6db0805cdcafb1312a91b60d14ff1ac24.tar.gz edk2-31f5ebd6db0805cdcafb1312a91b60d14ff1ac24.tar.bz2 edk2-31f5ebd6db0805cdcafb1312a91b60d14ff1ac24.zip | |
OvmfPkg/VmgExitLib: Check for an explicit DR7 cached value
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3108
Check the DR7 cached indicator against a specific value. This makes it
harder for a hypervisor to just write random data into that field in an
attempt to use an invalid DR7 value.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ard.biesheuvel@arm.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <65157c1155a9c058c43678400dfc0b486e327a3e.1610045305.git.thomas.lendacky@amd.com>
Diffstat (limited to 'BaseTools/Source/Python/CommonDataClass/FdfClass.py')
0 files changed, 0 insertions, 0 deletions