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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-05-25 17:00:16 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-05-28 14:59:19 +0800 |
| commit | 60cb4d1b04b6334cf9d56eb95d135546053db1fd (patch) | |
| tree | 02a4f428ef7a40ad8cc21b4996ac60da3d03b413 /BaseTools/Source/Python/Ecc/CParser.py | |
| parent | 36dd3c781e204a97d548ce3595ef6f6b6337bc1f (diff) | |
| download | edk2-60cb4d1b04b6334cf9d56eb95d135546053db1fd.tar.gz edk2-60cb4d1b04b6334cf9d56eb95d135546053db1fd.tar.bz2 edk2-60cb4d1b04b6334cf9d56eb95d135546053db1fd.zip | |
UefiCpuPkg/CpuCommonFeatures: Follow SDM for MAX CPUID feature detect
According to IA manual:
"Before setting this bit (MSR_IA32_MISC_ENABLE[22]) , BIOS must
execute the CPUID.0H and examine the maximum value returned in
EAX[7:0]. If the maximum value is greater than 2, this bit is
supported."
We need to fix our current detection logic to compare against 2.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Ming Shao <ming.shao@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Ecc/CParser.py')
0 files changed, 0 insertions, 0 deletions