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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-06-28 16:55:12 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2017-07-05 11:31:05 +0800 |
| commit | 5a4b3388aaca684db837fadf404c98852e8449c8 (patch) | |
| tree | 7b828f7881208998ba2e91f7e9a7b7d6590bfd4f /BaseTools/Source/Python/Ecc/Configuration.py | |
| parent | 1e6add9e476696461526163bde843570cfdffb39 (diff) | |
| download | edk2-5a4b3388aaca684db837fadf404c98852e8449c8.tar.gz edk2-5a4b3388aaca684db837fadf404c98852e8449c8.tar.bz2 edk2-5a4b3388aaca684db837fadf404c98852e8449c8.zip | |
MdeModulePkg/XhciDxe: Refine IsTransferRingTrb and IsAsyncIntTrb
Current implementation of IsTransferRingTrb only checks whether
the TRB is in the RING of the URB.
The patch enhanced the logic to check that whether the TRB belongs
to the transaction of URB.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Ecc/Configuration.py')
0 files changed, 0 insertions, 0 deletions