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| author | Feng Tian <feng.tian@intel.com> | 2016-09-14 09:48:40 +0800 |
|---|---|---|
| committer | Feng Tian <feng.tian@intel.com> | 2016-09-21 12:42:06 +0800 |
| commit | 1f87985ab7958664a84da78095b5892f88acf3f1 (patch) | |
| tree | 857c4f245ae09ade12cc9be55713838d815e7ce2 /BaseTools/Source/Python/Ecc/Database.py | |
| parent | dbe10619bc443215477c5c0c4c949410bf68b1ec (diff) | |
| download | edk2-1f87985ab7958664a84da78095b5892f88acf3f1.tar.gz edk2-1f87985ab7958664a84da78095b5892f88acf3f1.tar.bz2 edk2-1f87985ab7958664a84da78095b5892f88acf3f1.zip | |
MdeModulePkg/XhciPei:1ms delay before access MMIO reg during reset
Some XHCI host controllers require to have extra 1ms delay before
accessing any MMIO register during HC reset.
As this delay is not defined by XHCI spec, we use this workaround
to fix the issue.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Ecc/Database.py')
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