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author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-03-02 10:36:13 +0000 |
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committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-03-07 09:10:01 +0100 |
commit | df809efe13921326f2f8d7fc5654787b29ae8a8d (patch) | |
tree | 65347c3597b5808e096ee1eae01a82c7031aecc5 /BaseTools/Source/Python/Ecc/Exception.py | |
parent | 5b0ce08a3ee87a9d3fd3ecabfb1a94b5a209fb6c (diff) | |
download | edk2-df809efe13921326f2f8d7fc5654787b29ae8a8d.tar.gz edk2-df809efe13921326f2f8d7fc5654787b29ae8a8d.tar.bz2 edk2-df809efe13921326f2f8d7fc5654787b29ae8a8d.zip |
ArmPkg/CpuDxe ARM: avoid splitting page table sections unnecessarily
Currently, any range passed to CpuArchProtocol::SetMemoryAttributes is
fully broken down into page mappings if the start or the size of the
region happens to be misaliged relative to the section size of 1 MB.
This is going to result in memory being wasted on second level page tables
when we enable strict memory permissions, given that we remap the entire
RAM space non-executable (modulo the code bits) when the CpuArchProtocol
is installed.
So refactor the code to iterate over the range in a way that ensures
that all naturally aligned section sized subregions are not broken up.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'BaseTools/Source/Python/Ecc/Exception.py')
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