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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2020-02-26 10:54:04 +0100
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2020-03-05 21:08:30 +0000
commit02d7797d1a2c46ca140bade48aefb366813c2ce8 (patch)
tree815b0563d3ccd13983f8911f3c0ef39b77c87db9 /BaseTools/Source/Python/Ecc/ParserWarning.py
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ArmPkg/ArmMmuLib ARM: cache-invalidate initial page table entries
In the ARM version of ArmMmuLib, we are currently relying on set/way invalidation to ensure that the caches are in a consistent state with respect to main memory once we turn the MMU on. Even if set/way operations were the appropriate method to achieve this, doing an invalidate-all first and then populating the page table entries creates a window where page table entries could be loaded speculatively into the caches before we modify them, and shadow the new values that we write there. So let's get rid of the blanket clean/invalidate operations, and instead, invalidate each page table right after allocating it, and each section entry after it is updated (to address all the little corner cases that the ARMv7 spec permits), and invalidate sets of level 2 entries in blocks, using the generic invalidation routine from CacheMaintenanceLib On ARMv7, cache maintenance may be required also when the MMU is enabled, in case the page table walker is not cache coherent. However, the code being updated here is guaranteed to run only when the MMU is still off, and so we can disregard the case when the MMU and caches are on. Since the MMU and D-cache are already off when we reach this point, we can drop the MMU and D-cache disables as well. Maintenance of the I-cache is unnecessary, since we are not modifying any code, and the installed mapping is guaranteed to be 1:1. This means we can also leave it enabled while the page table population code is running. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
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