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| author | Chasel Chiu <chasel.chiu@intel.com> | 2020-06-04 14:43:40 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2020-06-23 04:22:49 +0000 |
| commit | 89f569ae8e759dc867009f396a516b7af5a3c0e7 (patch) | |
| tree | d28b5b1587b5c8b4f7a0f2c9c09f545cb3a3c2a6 /BaseTools/Source/Python/Ecc | |
| parent | 00b8bf7eda00fb6f0197d3968b6078cfdb4870fa (diff) | |
| download | edk2-89f569ae8e759dc867009f396a516b7af5a3c0e7.tar.gz edk2-89f569ae8e759dc867009f396a516b7af5a3c0e7.tar.bz2 edk2-89f569ae8e759dc867009f396a516b7af5a3c0e7.zip | |
IntelFsp2Pkg: Add FSP*_ARCH_UPD.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2781
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events
and multi-phase silicon initialization.
For backward compatibility the original structures are kept and
new ARCH_UPD structures will be included only when UPD header
revision equal or greater than 2.
GenCfgOpt script also updated to prevent from generating duplicate
FSPT_ARCH_UPD and FSPS_ARCH_UPD typedef structures.
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Ecc')
0 files changed, 0 insertions, 0 deletions