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| author | Ray Ni <ray.ni@intel.com> | 2022-07-18 16:41:37 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-09 07:08:05 +0000 |
| commit | 927113c83b4106aedf57fd1c8dc6dad5f1fe6a69 (patch) | |
| tree | bb181ab175024bad4ef8cec139f890ebab1c8ee0 /BaseTools/Source/Python/FirmwareStorageFormat/SectionHeader.py | |
| parent | 9f53fd4ba7ac4abe82365f310e0a4bcccc4448b3 (diff) | |
| download | edk2-927113c83b4106aedf57fd1c8dc6dad5f1fe6a69.tar.gz edk2-927113c83b4106aedf57fd1c8dc6dad5f1fe6a69.tar.bz2 edk2-927113c83b4106aedf57fd1c8dc6dad5f1fe6a69.zip | |
CpuPageTableLib: Fix bug that wrongly requires extra size for mapping
With following paging structure to map
[2M-4K, 2M] as P = 1, RW = 0,
[2M, 4M] as P = 1, RW = 1:
PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0)
-> PDE[1](RW = 1)
When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1,
CpuPageTableMap() wrongly requests 4K buffer size for the new mapping
request.
But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place,
for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already.
The change fixes the bug.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/FirmwareStorageFormat/SectionHeader.py')
0 files changed, 0 insertions, 0 deletions