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| author | Ray Ni <ray.ni@intel.com> | 2022-07-14 20:08:29 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-08-09 07:08:05 +0000 |
| commit | 9cb8974f06c6cc2545a66e696a58911122dec9fd (patch) | |
| tree | 02e9da1e6de12737b5cd0862c31c716aa4cb90ea /BaseTools/Source/Python/UPT/InventoryWs.py | |
| parent | 13a0471bfdcc1c7b18e182ca554d2ce98116e500 (diff) | |
| download | edk2-9cb8974f06c6cc2545a66e696a58911122dec9fd.tar.gz edk2-9cb8974f06c6cc2545a66e696a58911122dec9fd.tar.bz2 edk2-9cb8974f06c6cc2545a66e696a58911122dec9fd.zip | |
CpuPageTableLib: Split the page entry when LA is aligned but PA is not
When PageTableMap() is called to create non 1:1 mapping
such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the
4K page level, but old logic has a bug that it just uses 1G page
entry.
The patch fixes the bug.
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/UPT/InventoryWs.py')
0 files changed, 0 insertions, 0 deletions