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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-01-08 18:11:39 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-01-10 10:28:28 +0800 |
| commit | ffb4c72d7b637d4ac377fc7da7575069f15c288e (patch) | |
| tree | 6a3142cc513c2e0ac82466323ae4cd1977adf10e /BaseTools/Source/Python/UPT/Xml/ModuleSurfaceAreaXml.py | |
| parent | 5a6c5af64af9e6f5ea26a4c4682aed57c37c221c (diff) | |
| download | edk2-ffb4c72d7b637d4ac377fc7da7575069f15c288e.tar.gz edk2-ffb4c72d7b637d4ac377fc7da7575069f15c288e.tar.bz2 edk2-ffb4c72d7b637d4ac377fc7da7575069f15c288e.zip | |
UefiCpuPkg/MtrrLib: Fix bug that may calculate wrong MTRR result
Code forgot to initialize the optional weight between adjacent
vertices. It caused wrong MTRR result was calculated for some
memory settings.
The logic was incorrectly removed when converting from POC
code. The patch adds back the initialization.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/UPT/Xml/ModuleSurfaceAreaXml.py')
0 files changed, 0 insertions, 0 deletions