summaryrefslogtreecommitdiffstats
path: root/BaseTools/Source/Python/UPT
diff options
context:
space:
mode:
authorRay Ni <ray.ni@intel.com>2022-07-14 18:00:47 +0800
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2022-08-09 07:08:05 +0000
commit13a0471bfdcc1c7b18e182ca554d2ce98116e500 (patch)
tree6df2991f58367a596a0dde27e0a2c458af37601d /BaseTools/Source/Python/UPT
parentbf334513b3eb02ef98e5b38e0b7b5d7408492fdd (diff)
downloadedk2-13a0471bfdcc1c7b18e182ca554d2ce98116e500.tar.gz
edk2-13a0471bfdcc1c7b18e182ca554d2ce98116e500.tar.bz2
edk2-13a0471bfdcc1c7b18e182ca554d2ce98116e500.zip
CpuPageTableLib: Refactor the logic
The patch replaces LinearAddress + Offset == RegionStart with ((LinearAddress + Offset) & RegionMask) == 0 The replace should not cause any behavior change. Because: 1. In first loop of while when LinearAddress + Offset == RegionStart, because the lower "BitStart" bits of RegionStart are all-zero, all lower "BitStart" bits of (LinearAddress + Offset) are all-zero. Because all lower "BitStart" bits of RegionMask is all-one and bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0. 2. In following loops of the while, even RegionStart is increased by RegionLength, the lower "BitStart" bits are still all-zero. So the two expressions still semantically equal to each other. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/UPT')
0 files changed, 0 insertions, 0 deletions