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author | Dandan Bi <dandan.bi@intel.com> | 2018-01-17 09:47:58 +0800 |
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committer | Liming Gao <liming.gao@intel.com> | 2018-02-08 12:50:20 +0800 |
commit | 9e62c230170c96f16d9c5d46e100683ef3ccefb7 (patch) | |
tree | ba79ee55bd964291296551fc4a7fb80cf95ca7f6 /BaseTools/Source/Python/Workspace/BuildClassObject.py | |
parent | 2040e6c556e0f39236fc9bc1cfca61afe9dad3bf (diff) | |
download | edk2-9e62c230170c96f16d9c5d46e100683ef3ccefb7.tar.gz edk2-9e62c230170c96f16d9c5d46e100683ef3ccefb7.tar.bz2 edk2-9e62c230170c96f16d9c5d46e100683ef3ccefb7.zip |
MdeModulePkg/FirmwarePerfDxe:Enhance for new pref infrastructure
V4:
Update the GUID for status code in DxeCorePerformanceLib and
FirmwarePerformanceDxe.
V3:Add handling for the case when performance feature is not enabled.
V2:
Update FirmwarePerformanceDxe to receive the address
of performance records instead of records content.
1. Remove the macro EXTENSION_RECORD_SIZE, since the extension
size can be got through PcdExtFpdtBootRecordPadSize.
2. Hook EFI_SW_DXE_BS_PC_READY_TO_BOOT_EVENT to install ACPI table
3. Copy SMM record accord to the allocated size
4. Receive Boot performance table address instead of
contents which are reported DxeCorePerformanceLib.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace/BuildClassObject.py')
0 files changed, 0 insertions, 0 deletions