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| author | Tomasz Michalec <tm@semihalf.com> | 2018-09-18 16:59:06 +0800 |
|---|---|---|
| committer | Hao Wu <hao.a.wu@intel.com> | 2018-09-21 10:47:47 +0800 |
| commit | 064d301fb07566ab6d3d89010b9666f320698f34 (patch) | |
| tree | 233023ee7e4b8bbba3bfe1f0159b668bdd065c7e /BaseTools/Source/Python/Workspace/DscBuildData.py | |
| parent | 9062ab47870ea728307e32cdd939586a4ec67fc6 (diff) | |
| download | edk2-064d301fb07566ab6d3d89010b9666f320698f34.tar.gz edk2-064d301fb07566ab6d3d89010b9666f320698f34.tar.bz2 edk2-064d301fb07566ab6d3d89010b9666f320698f34.zip | |
MdeModulePkg/SdMmcPciHcDxe: Fix SdMmcHcReset to set only necesery bits
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1185
SdMmcHcReset used to set all bits of Software Reset Register to 1
including reserved ones, which on some controllers may result in
timeout.
Now only first bit is set, which means "Software Reset for All".
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace/DscBuildData.py')
0 files changed, 0 insertions, 0 deletions