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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-02-06 15:26:41 +0800 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-02-08 13:49:06 +0800 |
| commit | 0c8b88022372846a377c424f46e671d8868d4ece (patch) | |
| tree | 8658f7c4353bc3e1f4c49cfab489fc44c6a7a004 /BaseTools/Source/Python/Workspace/DscBuildData.py | |
| parent | 115eae650bfd2be2c2bc37360f4a755065e774c4 (diff) | |
| download | edk2-0c8b88022372846a377c424f46e671d8868d4ece.tar.gz edk2-0c8b88022372846a377c424f46e671d8868d4ece.tar.bz2 edk2-0c8b88022372846a377c424f46e671d8868d4ece.zip | |
UefiCpuPkg/FeaturesLib: Fix Haswell CPU hang with 50% throttling
Today's implementation only assumes SandyBridge CPU supports
Extended On-Demand Clock Modulation Duty Cycle.
Actually it is supported when CPUID.06h.EAX[5] == 1.
When platform requests 50% throttling, it causes value 1000b
set to the low-4 bits of IA32_CLOCK_MODULATION.
But the wrong code sets 1000b to bits[1-3] which causes assertion.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <vanjeff_919@hotmail.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace/DscBuildData.py')
0 files changed, 0 insertions, 0 deletions