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author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-08-24 13:20:32 +0800 |
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committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-08-31 10:40:15 +0800 |
commit | 54ee6176eda4f6ae1d27d53c00818e350db93f97 (patch) | |
tree | b16aea917ebceae10d3eb17bd32485290b07f0c5 /BaseTools/Source/Python/Workspace/DscBuildData.py | |
parent | f89c018f3dec056e28d38686ba0778597227949e (diff) | |
download | edk2-54ee6176eda4f6ae1d27d53c00818e350db93f97.tar.gz edk2-54ee6176eda4f6ae1d27d53c00818e350db93f97.tar.bz2 edk2-54ee6176eda4f6ae1d27d53c00818e350db93f97.zip |
EmulatorPkg/AutoScanPei: Report the correct CPU address size
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1119
Today's implementation reports CPU address size as 36 through CPU
HOB. But when WinHost is running at 64bit, the system memory might
be allocated above 2^36.
It causes system asserts when DxeCore code tries to find the
corresponding GCD entry for a given valid address.
The patch uses 57 as the CPU address size which is maximum linear
address size when 5-level paging is enabled in host OS.
Using 64 seems more proper and a one-time change even 6-level
paging might be invented. But it causes CoreInitializeGcdServices()
assertion on following code:
Entry->EndAddress = LShiftU64 (1, SizeOfMemorySpace) - 1;
Because LShiftU64 expects SizeOfMemorySpace < 64.
So to be practical, I didn't report 64 and change
CoreInitializeGcdServices().
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
Cc: Andrew Fish <afish@apple.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace/DscBuildData.py')
0 files changed, 0 insertions, 0 deletions